1. Field of the Invention
The present invention relates generally to hybrid memory made of magnetic memory and conventional random access memory (RAM), flash-RAM, exhibiting volatile and non-volatile magnetic memory characteristics and particularly to flash-RAM including stackable non-volatile magnetic memory.
2. Description of the Prior Art
Computers conventionally use rotating magnetic media, such as hard disk drives (HDDs), for data storage. Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, higher power dissipation, large physical size and inability to withstand any physical shock. Thus, there is a need for a new type of storage device devoid of such drawbacks.
Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read/write access time, and solid state storage, such as solid-state-nonvolatile-memory (SSNVM) devices. SSNVM devices have memory structures made of NOR/NAND-based flash memory, providing fast access time, increased input/output (JO) speed, decreased power dissipation and physical size and increased reliability but at a higher cost which tends to be generally multiple times higher than hard disk drives (HDDs).
Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected. However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions. For example, NAND-based flash memory has issues related to capacitive coupling, few electrons/bit, poor error-rate performance and reduced reliability due to decreased read-write endurance. Read-write endurance refers to the number of reading, writing and erase cycles before the memory starts to degrade in performance due primarily to the high voltages required in the program, erase cycles.
It is believed that NAND flash would be extremely difficult to scale below 45 nanometers (nm). Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.
Currently, applications commonly employ combinations of EEPROM/NOR, NAND, HDD, and DRAM memory in a system design. Design of different memory technology in a product adds to design complexity, time to market and increased costs. For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM/NOR flash memory, complexity of design is increased as are manufacturing costs and time to market. Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.
There has been an extensive effort in development of alternative technologies, such as Ovanic Ram (or phase-change memory), Ferro-electric Ram (FeRAM), Magnetic Ram (MRAM), Nanochip, and others to replace memories used in current designs such as DRAM, SRAM, EEPROM/NOR flash, NAND flash and HDD in one form or another. Although these various memory/storage technologies have created many challenges, there have been advances made in this field in recent years. MRAM seems to lead the way in terms of its progress in the past few years to replace all types of memories in the system as a universal memory solution.
One of the problems with prior art memory structures including MRAMs is their cell or memory size being too large therefore not lending itself well to scalability. A typical design of such MRAMs uses one or more transistors for one memory cells that lead to nT-1 mem cell type design where n=1−6. This makes the cell size too large leading to issues of scalability and cost. Recently, current-induced magnetization switching (CIMS) is being explored as an alternative memory solution, and allegedly introduces a better way of building higher capacity MRAM type memory. But memories based on MRAM tend to have larger cell size (16-24 F2, where F is the minimum feature based on the lithography technology).
Therefore, in light of the foregoing, what is needed is a non-volatile magnetic memory element utilizing magnetic diodes for addressing memory cells, the memory cells capable of being stacked on top of each other (in the direction of the z-axis) enabling higher capacity, lower cost designs and scalability (independent of lithography limits).
In recent years, flash memory has become the non-volatile memory of choice for a number of mobile hand-held devices such as, the Multi-Player (MP) 3-players, digital cameras, cell-phones, hand-held computers. This is primarily due to a dramatic drop in the price of the flash memory. Flash memory is typically made using two designs namely, NAND or NOR. NOR flash is faster than NAND flash, while NAND flash has higher density. NOR flash memories are primarily used for applications where non-volatility is essential, but the size of the memory is small and the memory is seldom read or written. NAND on the other hand is used where a huge amount of memory is needed. The slow write and memory degradation due to write and erase are masked by clever designs. Both of these types of flash can have more than one bit of data stored in one cell. This is called MLC flash. This is mostly used in NAND flash to enhance the memory density, but normally adversely affects the speed of the memory.
Another form of dominant memory is the dynamic RAM (DRAM), which is volatile and costly but has faster random read/write time than non-volatile memory in the form of flash. From a cost perspective, MLC NAND is the cheapest, followed by NAND, then NOR, and then DRAM. Static RAM is the most expensive memory used.
In the current marketplace, NOR tends to be approximately five times more costly than MLC NAND, due primarily to its cell size. A typical size for a NOR memory cell is about 10-12 F2 vs. about 2.5 F2 for a NAND cell. DRAM has a cell size of 8 F2 but is harder to manufacture due to its various trench-capacitor design requirements. Additionally, as the process geometry decreases, the design of NAND and DRAM memory become more difficult to scale. For example, NAND has various issues related to capacitive coupling, fewer electrons/bit, poor error-rate performance and worse reliability due to its poor read-write endurance. It is believed that NAND, especially MLC NAND would be extremely difficult to scale below 45 nano meters (nm). Likewise, DRAM has issues related to scaling of its trench capacitors leading to very complex designs which are becoming very difficult to manufacture, thereby leading to increased manufacturing costs.
FIG. 1A shows a prior art system including a host, or central processing unit (CPU) 600 coupled to transfer information to and from non-volatile memory 602 (or read-only memory (ROM) and RAM), which may be in the form of NOR or NAND and further coupled to volatile memory 604, such as DRAM. In some systems, non-volatile memory 602 includes both NOR and NAND. Current high performance systems, such as that of FIG. 1A require capability for loading boot code and operating system (OS) code. The boot code typically resides in non-volatile memory 602 while the operating system (OS) code typically resides on a hard disk drive and is downloaded onto the DRAM 604 and/or NAND when the non-volatile memory 602 includes NAND as well.
In general, a combination of NOR, NAND and DRAM is used for functioning as both RAM and ROM, reducing the overall cost of the memory system. This is a dominant part of the overall cost for mobile multi-media products. This group of memory products is referred to as “hybrid-flash.” Table 2 shows speed performances of hybrid flash products currently available in the market. The type and size, as well as architecture of these products are generally different, resulting in different overall timing performance, For example, the one-NAND product, manufactured by Samsung Electronics of South Korea has a smaller-sized DRAM, but the architecture and design are such that it results in higher write speed while maintaining lower cost. Depending upon the application, the system designers may choose to include additional DRAM in order to improve the overall system performance. There are a number of other such products by various manufacturers for this fast growing segment of the market, driven by the insurgence of various hand-held mobile devices.
In FIG. 1A, application code is shadowed (or copied) from non-volatile memory 602 to volatile memory 604 which then carries out the operations with the operating system.
The problem with all of the currently available hybrid designs is the large size and therefore high costs and high power consumption associated therewith. That is, ROM and RAM are manufactured on multiple chips, and perhaps a monolithic die, resulting in larger real estate being consumed by use of such memory, and therefore increased costs. In some examples, one unit of the memory capacity of a typical “hybrid-flash” product today is made of DRAM for every two units of NAND, i.e. 512 MB of DRAM for every 1 GB of NAND. This capacity usage on a printed circuit board (PCB) that additionally has other chips (or semiconductor), such as a controller, make such designs approximately 5 to 10 times more expensive than the NAND memory.
Additionally, power consumption is high due to the operations of non-volatile and volatile memory, of which the volatile memory has to stay on the standby power all the time.
Accordingly, the need arises for a hybrid memory including both volatile and non-volatile memory that is lower in power consumption, less costly to manufacture, and occupies less space.